1. Field of the Invention
The present invention relates to an integrated circuit provided with an active element, such as a CMOS (complementary metal oxide semiconductor), a TFT (thin film transistor), or the like, and provided with an inductor as well as to a manufacturing method for the same, in particular, relates to an integrated circuit wherein an increase in speed of an active element is achieved and wherein an improvement in the characteristics of an inductor is achieved as well as to a manufacturing method thereof.
2. Description of the Related Art
An integrated circuit provided with an active element, such as a CMOS, a TFT, or the like, wherein an inductor has conventionally been fabricated on a standard substrate and an epitaxial layer including P type impurities is formed on a P+ bulk substrate.
FIG. 1 is a cross sectional view showing a conventional integrated circuit. A standard substrate wherein a P− epitaxial layer 52 is formed on a P+ bulk substrate 51 is utilized for the substrate of this integrated circuit according to the prior art. The P+ bulk substrate 51 has a resistivity of approximately 0.01Ω· cm and a thickness of approximately 700 .m while the P− epitaxial layer 52 has a resistivity of approximately 10 Ω· cm and a thickness of approximately 5 μm. A CMOS 55, which is an active element, is provided in a portion of a region in the surface of the P− epitaxial layer 52 and the CMOS 55 includes a P well 53 and an N well 54. An insulating film 56 is provided in a region of the P− epitaxial layer 52 wherein the CMOS 55 is not provided and an insulating film 57 is provided on the CMOS 55 and the insulating film 56. An inductor 58 is provided on the portion of the region of the insulating film 57 corresponding to the insulating film 56. In the integrated circuit shown in FIG. 1, latch-up is suppressed in the CMOS 55 and gathering of impurities in the CMOS 55 can be promoted by utilizing the standard substrate made of the P+ bulk substrate 51 and the P− epitaxial layer 52.
In this conventional integrated circuit shown in FIG. 1, however, the resistivity of the P+ bulk substrate 51 has a low value of approximately 0.01 Ω·cm and, therefore, an eddy current flows within the P+ bulk substrate 51 so that a problem arises wherein an eddy current loss occurs at the time of operation of the inductor 58. As a result, the Q value of the inductor 58 is lowered so that the characteristics of the inductor 58 deteriorate. In addition, a parasitic capacitance occurs between the inductor 58 and the P+ bulk substrate 51 so that the characteristics of the inductor 58 deteriorate. Furthermore, a parasitic capacitance also occurs between the CMOS 55 and the P+ bulk substrate 51 so that a problem arises wherein increase in the speed of the CMOS 55 cannot be achieved.
A technique wherein a trench is created in the surface layer of a substrate under an inductor and an insulating material is filled into this trench is disclosed in Japanese Patent Application Laid-open No. 321802/1998. Thereby, the path of an eddy current can be shortened so that the occurrence of an eddy current can be suppressed, according to the description therein.
In addition, a technique similar to that of Japanese Patent Application Laid-open No. 321802/1998 wherein a trench is created in the surface layer of a substrate under an inductor and an insulating material is filled into this trench is disclosed in Japanese Patent Application Laid-open No. 274412/1999. Thereby, the effective surface area of the substrate can be reduced so that the parasitic capacitance is reduced according to the description therein.
The above-described conventional technologies, however, have problems as shown below. It is extremely difficult to create a deep trench according to the technologies disclosed in Japanese Patent Application Laid-open No. 321802/1998 and in Japanese Patent Application Laid-open No. 274412/1999. Therefore, a sufficiently deep trench cannot be created according to these technologies and an insulating film having a thickness sufficient to significantly improve the characteristics of an inductor cannot be created. Accordingly, the effects obtained according to the technique disclosed in Japanese Patent Application Laid-open No. 321802/1998 are not sufficient to improve the characteristics of an inductor. In addition, an increase in speed of an active element cannot be achieved according to this technique. In addition, an insulating film having a sufficient thickness cannot be created according to the technique disclosed in Japanese Patent Application Laid-open No. 274412/1999 and, therefore, effects are insufficient to improve the characteristics of an inductor. In addition, an increase in speed of an active element cannot be achieved according to this technique. Accordingly, the characteristics of an active element and an inductor cannot be significantly improved even in the case wherein the technologies disclosed in Japanese Patent Application Laid-open No. 321802/1998 and Japanese Patent Application Laid-open No. 274412/1999 are applied.